MT42L256M32D4KP-3 IT:A【PDF 74/164 页】IC LPDDR2 SDRAM 8GBIT 168FBGA

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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

REFRESH Command

Table 43: PRECHARGE and Auto Precharge Clarification (Continued)

From

Command

To Command

Minimum Delay Between Commands

Unit

Notes

WRITE w/AP PRECHARGE to same bank as WRITE w/AP

WL + BL/2 + RU( t WR/ t CK) + 1

CLK

1, 2

PRECHARGE ALL

WL + BL/2 +

RU( t WR/ t CK)

+1

CLK

1

ACTIVATE to same bank as WRITE w/AP

WL + BL/2 +

RU( t WR/ t CK)

+1+

RU( t RPpb/ t CK)

CLK

1

WRITE or WRITE w/AP (same bank)

WRITE or WRITE w/AP (different bank)

READ or READ w/AP (same bank)

Illegal

BL/2

Illegal

CLK

CLK

CLK

3

3

3

READ or READ w/AP (different bank)

PRECHARGE PRECHARGE to same bank as PRECHARGE

PRECHARGE ALL

PRECHARGE PRECHARGE

ALL

PRECHARGE ALL

WL + BL/2 +

1

1

1

1

RU( t WTR/ t CK)

+1

CLK

CLK

CLK

CLK

CLK

3

1

1

1

1

Notes:

1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE

command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank.

The PRECHARGE period is satisfied after t RP, depending on the latest PRECHARGE com-

mand issued to that bank.

2. Any command issued during the specified minimum delay time is illegal.

3. After READ with auto precharge, seamless READ operations to different banks are sup-

ported. After WRITE with auto precharge, seamless WRITE operations to different banks

are supported. READ with auto precharge and WRITE with auto precharge must not be

interrupted or truncated.

REFRESH Command

The REFRESH command is initiated with CS# LOW, CA0 LOW, CA1 LOW, and CA2 HIGH

at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at the ris-

ing edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising edge of

the clock. Per-bank REFRESH is only supported in devices with eight banks.

A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to

the bank scheduled by the bank counter in the memory device. The bank sequence for

per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The

bank count is synchronized between the controller and the SDRAM by resetting the

bank count to zero. Synchronization can occur upon issuing a RESET command or at

every exit from self refresh. Bank addressing for the per-bank REFRESH count is the

same as established for the single-bank PRECHARGE command (see Table 42

(page 69)).

A bank must be idle before it can be refreshed. The controller must track the bank being

refreshed by the per-bank REFRESH command.

The REFpb command must not be issued to the device until the following conditions

have been met:

? t RFCab has been satisfied after the prior REFab command

? t RFCpb has been satisfied after the prior REFpb command

? t RP has been satisfied after the prior PRECHARGE command to that bank

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

74

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2010 Micron Technology, Inc. All rights reserved.

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MT42L256M32D4KP-MS 制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk